1. Field of the Invention
The present invention relates to discrete or integrated circuit semiconductor devices and a method of manufacturing the same.
2. Description of the Background Art
FIG. 20 shows a cross section of a background art output transistor. The output transistor of FIG. 20 comprises an n+ semiconductor substrate 1b, an nxe2x88x92 epitaxial layer 2b, p-type diffusion regions 191, n+ diffusion regions 193 formed in the respective surfaces of the p-type diffusion regions 191, a control electrode 291, an insulation film 3b surrounding the control electrode 291, a source electrode 293 in contact with the insulation film 3b, the p-type diffusion regions 191 and the n+ diffusion regions 193, and a drain electrode 292 in contact with the bottom surface of the semiconductor substrate 1b. 
In the structure shown in FIG. 20, the p-type diffusion regions 191 and the n+ diffusion regions 193 are formed using the insulation film 3b as a mask. The difference in lateral diffusion length between the p-type diffusion regions 191 and the n+ diffusion regions 193 defines MOS channels CH.
The structure of FIG. 20 is known as a DMOS (Double diffused MOS) transistor. The DMOS transistor which uses the nxe2x88x92 epitaxial layer 2b as an offset drain has a reduced gate length independently of photolithographic precision and can ensure the uniformity of the gate length. Therefore, DMOS transistors are most commonly used as high breakdown voltage devices which require low on-resistance.
A significant aim of the DMOS transistors is to improve a tradeoff between breakdown voltage and on-resistance. To achieve this aim, generally two approaches to such an improvement have been made.
The first approach is to increase the mask alignment precision of a stepper to reduce the size of devices, thereby improving the tradeoff between breakdown voltage and on-resistance.
The second approach is to shorten a channel length by making the p-type diffusion regions 191 and the n+ diffusion regions 193 shallower to reduce a JFET resistance between the pair of p-type diffusion regions 191, thereby improving the tradeoff between breakdown voltage and on-resistance.
However, the first approach provides an improvement effect which substantially reaches a point of saturation since the precision of mask alignment at the current level may be considered equivalent to the processing precision of an entire process. Therefore, the first approach is not expected to provide a further considerable improvement in the tradeoff between breakdown voltage and on-resistance.
It is hence considered to apply the second approach to the first approach. Unfortunately, the second approach can reduce the channel length and the JFET resistance, but is not capable of suppressing the increase in curvature of a diffusion corner. The increase in curvature of a diffusion corner decreases the breakdown voltage. Thus, the application of the second approach to the first approach encounters limitation of the improvement in the tradeoff between breakdown voltage and on-resistance.
According to a first aspect of the present invention, a semiconductor device comprises: a semiconductor layer including a main surface, a first region of a first conductivity type, a second region of a second conductivity type, and a third region of the second conductivity type, the first region and the second region having a first boundary formed therebetween, the first boundary being perpendicular to the main surface, the third region being formed in the first region in spaced apart relation to the second region, the third region having a depth less than the depth of the first boundary from the main surface; and a control electrode insulated from and overlying the main surface and extending from the first boundary to a second boundary formed between the first region and the third region.
Preferably, according to a second aspect of the present invention, in the semiconductor device of the first aspect, the first region has an impurity concentration decreasing with increase in distance from the main surface of the semiconductor layer.
Preferably, according to a third aspect of the present invention, in the semiconductor device of the first aspect, the main surface has a polygonal plan configuration, and the first region is disposed at a vertex of the polygonal plan configuration.
According to a fourth aspect of the present invention, a method of manufacturing a semiconductor device comprises the steps of: (a) implanting a first impurity of a first conductivity type and a second impurity of a second conductivity type into a first region formed in a main surface of a semiconductor layer and a second region adjacent to the first region, respectively; (b) heat-treating a resultant structure provided in the step (a) to diffuse the first and second impurities; and (c) forming a third region of the second conductivity type in the main surface in the first region in spaced apart relation to the second region, and forming a control electrode insulated from and overlying the main surface, the control electrode extending from a first boundary formed between the first and second regions to a second boundary formed between the first and third regions.
Preferably, according to a fifth aspect of the present invention, in the method of the fourth aspect, the step (a) comprises the steps of: (a-1) covering at least the first and second regions in the main surface of the semiconductor layer with an oxide film; (a-2) covering part of the oxide film which overlies at least one of the first and second regions with a mask; (a-3) implanting one of the first and second impurities into the other of the first and second regions, the step (a-3) being performed after the step (a-2); (a-4) oxidizing part of the oxide film which is exposed over the other of the first and second regions to increase the thickness of the part of the oxide film, the step (a-4) being performed after the step (a-3); (a-5) removing the mask, the step (a-5) being performed after the step (a-4); and (a-6) implanting the other of the first and second impurities into the one of the first and second regions, the step (a-6) being performed after the step (a-5). The method further comprises the step of (d) removing the oxide film, the step (d) being performed prior to the step (c).
In accordance with the first aspect of the present invention, the first boundary between the first and second regions is perpendicular to the main surface to suppress the decrease in breakdown voltage. Additionally, the second region of the second conductivity type may greatly reduce on-resistance. Therefore, the present invention improves a tradeoff between breakdown voltage and on-resistance.
In accordance with the second aspect of the present invention, if a diffusion corner having a great curvature is developed at the bottom of the first region, the low concentration of the first impurity in the first region may suppress the decrease in the breakdown voltage.
In accordance with the third aspect of the present invention, the boundary between the first and second region contains at least the first boundary. This accordingly alleviates electric field concentration to render the semiconductor device less susceptible to breakdown.
In accordance with the fourth aspect of the present invention, the first boundary perpendicular to the main surface of the semiconductor layer is formed between the first and second regions. Additionally, the concentrations of the first and second impurities in the first and second regions decrease with the increase in distance from the main surface of the semiconductor layer. Therefore, if a diffusion corner having a great curvature is developed at the bottom of the first region, the semiconductor device in which the decrease in breakdown voltage is suppressed is achieved.
In accordance with the fifth aspect of the present invention, a bird""s beak is formed additionally in the step (a-4). A region immediately under the bird""s beak contains few first and second impurities. The presence of a gap containing few impurities prevents the position of the first boundary between the first and second regions from being shifted out of the region immediately under the bird""s beak, to provide the first boundary which is substantially stable and planar.
It is therefore an object of the present invention to provide a novel semiconductor device which improves a tradeoff between breakdown voltage and on-resistance, and a method of manufacturing the same.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.